Jitter applying circuit and test apparatus

Details Jitter applying circuit and test apparatus Jitter applying circuit and test apparatus

2007-10-23

2007-10-23

Britt, Cynthia (Department: 2117)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Skew detection correction

C714S798000, C327S158000

Reexamination Certificate

active

11178226

ABSTRACT:
There is provided a jitter application circuit for generating a clock signal containing a phase jitter component corresponding to given jitter data, having a PLL circuit for generating an oscillating signal corresponding to a given reference signal, a variable delay circuit for outputting said clock signal in which said oscillating signal is delayed, a low-frequency application section for applying low-frequency component of said phase jitter component to said oscillating signal by controlling oscillation frequency of said PLL circuit based on the low-frequency component of said jitter data and a high-frequency application section for applying high-frequency component of said phase jitter component to said clock signal by controlling a delay in said variable delay circuit based on the high-frequency component of said jitter data.

REFERENCES:
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patent: 6621352 (2003-09-01), Matsumoto et al.
patent: 6686879 (2004-02-01), Shattil
patent: 7142624 (2006-11-01), Cranford et al.
patent: 2003/0231707 (2003-12-01), French et al.
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patent: 6-104708 (1994-04-01), None
patent: 6-112785 (1994-04-01), None
patent: 2002124873 (2002-04-01), None
Alvarez et al. A wide-bandwidth low-voltage PLL for Power PCTM microprocessors, Solid-State Circuits, IEEE Journal of vol. 30, Issue 4, Apr. 1995 pp. 383-391.
International Search Report dated Aug. 2, 2005 (2 pages).

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