Testing the interrupt sources of a microprocessor

Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability

Reexamination Certificate

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Details

C710S104000, C710S048000, C710S260000

Reexamination Certificate

active

10293902

ABSTRACT:
A method of testing the interrupt sources of a microprocessor having a number of interrupts which are each operable to execute an interrupt service routine when enabled, each interrupt having a default priority level and an associated memory, the interrupts having a service order in which they are to be serviced, the method comprising the steps of: a) sorting the interrupts in descending service order; b) determining an array of priority levels to be assigned in a pre-arranged sequence to selections of interrupts in descending service order, the array of priority levels consisting of: the lowest priority level; and the priority levels in descending order from the highest priority level to the lowest priority level; c) incrementing a global counter; d) assigning the array of priority levels to a selected group of interrupts, the remainder of the interrupts assuming their pre-assigned priority level; e) enabling all interrupts simultaneously so that the interrupt having the highest priority level executes its interrupt service routine; f) transferring the value of the global counter into the memory of the interrupt having executed its interrupt service routine; g) repeating steps c) to f) until the pre-arranged sequence is completed; and h) comparing the interrupt memory values after completion of the pre-arranged sequence with expected values and determining from the comparison whether there is an error in the microprocessor interrupts.

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