Process for patterning metal connections on a semiconductor stru

Details Process for patterning metal connections on a semiconductor stru Process for patterning metal connections on a semiconductor stru

1980-06-09

1981-09-15

Smith, John D.

Adhesive bonding and miscellaneous chemical manufacture

Delaminating processes adapted for specified product

Delaminating in preparation for post processing recycling step

148 63, 156650, 156665, 156667, 427 88, 427 90, 4271264, 430318, H01L 2128, C23F 102

Patent

active

042895740

ABSTRACT:
A process for patterning plasma etchable regions on a semiconductor structure includes the steps of forming a layer of an oxide of aluminum over the surface of the semiconductor structure, forming an overlying layer of plasma etchable material on the layer of oxide, and removing undesired portions of the overlying layer by plasma etching to thereby expose portions of the layer of oxide. In some embodiments of the invention the thereby exposed portions of the layer of oxide are then removed, together with any underlying portions of the first layer, by isotropic etching.

REFERENCES:
patent: 4030967 (1977-06-01), Ingrey
patent: 4057460 (1977-11-01), Saxena
patent: 4092210 (1978-05-01), Hoepfner
patent: 4135954 (1979-01-01), Chang
patent: 4157269 (1979-06-01), Ning
Johnson et al., "Etch Stop for Reactive Ion Etching of Polysilicon", IBM TDB 21, No. 2, p. 599, Jul. 1978.
Schaible et al., "Reactive Ion Etching of Aluminum and Aluminum Alloys", IBM TDB, 21, No. 4, Sep. 1978.

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