Method and apparatus for facilitating effective and...

Details Method and apparatus for facilitating effective and... Method and apparatus for facilitating effective and...

2007-08-14

2007-08-14

Garbowski, Leigh M. (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000, C716S030000

Reexamination Certificate

active

10876699

ABSTRACT:
Methods and apparatuses are disclosed to facilitate routing between a first and second component in a programmable logic device to generate a path with an appropriate amount of delay to satisfy short-path timing constraints efficiently and effectively.

REFERENCES:
patent: 5212652 (1993-05-01), Agrawal et al.
patent: 5260611 (1993-11-01), Cliff et al.
patent: 5815003 (1998-09-01), Pedersen
patent: 6130551 (2000-10-01), Agrawal et al.
patent: 6181163 (2001-01-01), Agrawal et al.

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