Electrical computers and digital processing systems: processing – Processing control – Processing control for data transfer
Reexamination Certificate
2007-08-21
2007-08-21
Kim, Kenneth S. (Department: 2111)
Electrical computers and digital processing systems: processing
Processing control
Processing control for data transfer
C713S001000
Reexamination Certificate
active
11091584
ABSTRACT:
A processor (1) having an instruction memory (2) supplies addressing information and setting values to be set to registers (REGA to REGD) to a setting interface unit (3), and address values of the registers are outputted from an address output unit (5) based on the addressing information. The outputted address values and the setting values are outputted respectively to registers to set setting values, so that the processor can set the setting values to be set to the registers without being conscious of the addresses of the registers, and thus it becomes possible to reduce addressing portions of the respective registers in the instruction codes, and reduce the number of instruction codes, which facilitates coding of the instruction codes.
REFERENCES:
patent: 6820191 (2004-11-01), Guey et al.
patent: 2003/0135528 (2003-07-01), Choi et al.
patent: 2-5115 (1990-01-01), None
patent: 9-6483 (1997-01-01), None
patent: 2001-22685 (2001-01-01), None
Abstract of JP-2001-101072A published Apr. 13, 2001 in Japan.
Abstract of JP-08-153001A published Jun. 11, 1996 in Japan.
Ikeda Norihiro
Kanasugi Masami
Kuroiwa Koichi
Taniguchi Shoji
Arent & Fox LLP
Fujitsu Limited
Kim Kenneth S.
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