Flash memory device

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

Reexamination Certificate

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C257S316000

Reexamination Certificate

active

10838215

ABSTRACT:
A non-volatile memory device includes a substrate, an insulating layer, a fin structure, a floating gate, an inter-gate dielectric and a control gate. The insulating layer is formed on the substrate and the fin structure is formed on the insulating layer. The fin structure may include a strained layer formed on a non-strained layer.

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patent: 6963104 (2005-11-01), Wu et al.
patent: 2003/0178670 (2003-09-01), Fried et al.
patent: 2005/0242388 (2005-11-01), Willer et al.
Digh Hisamoto et al., “FinFET-A Self-Aligned Double-Gate MOSFET Scalable to 20 nm,” IEEE Transactions on Electron Devices, vol. 47, No. 12, Dec. 2000, pp. 2320-2325.
Yang-Kyu Choi et al., “Sub-20nm CMOS FinFET Technologies,” 2001 IEEE, IEDM, pp. 421-424.
Xuejue Huang et al., “Sub-50 nm P-Channel FinFET,” IEEE Transactions on Electron Devices, vol. 58, No. 5, May 2001, pp. 880-886.
Xuejue Huang et al., “Sub 50-nm FinFET: PMOS,” IEEE, IEDM, pp. 67-70.
Yang-Kyu Choi et al., “Nanoscale CMOS Spacer FinFET for the Terabit Era,” IEEE Electron Device Letters, vol. 23, No. 1, Jan. 2002, pp. 25-27.
Co-pending U.S. Appl. No. 10/929,538 by Yu et al., filed Aug. 31, 2004, entitled “Non-Volatile Memory Device”, 25 pages.

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