PMOS device with drain junction breakdown point located for...

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

Reexamination Certificate

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C257S355000

Reexamination Certificate

active

10825833

ABSTRACT:
A PMOS device can be designed and manufactured in accordance with the invention to locate its drain junction breakdown point and maximum impact ionization point to reduce or eliminate drain breakdown voltage walk-in. In some embodiments, the drain junction breakdown point and maximum impact ionization point are located sufficiently far from the gate that the device exhibits no significant drain breakdown voltage walk-in. The device can be a high voltage power transistor having an extended drain region including a P-type lightly doped drain (P-LDD) implant, with drain junction breakdown and maximum impact ionization points appropriately located by controlling the implant dose employed to produce the P-LDD implant. Other aspects of the invention are methods for designing a PMOS device including by determining relative locations of the gate and at least one of the drain junction breakdown and maximum impact ionization points to reduce drain breakdown voltage walk-in, and methods for manufacturing integrated circuits including any embodiment of the PMOS device of the invention.

REFERENCES:
patent: 5306652 (1994-04-01), Kwon et al.
patent: 2003/0011039 (2003-01-01), Ahlers et al.
patent: 2003/0122195 (2003-07-01), Tada et al.
D. Brisbin, A. Strachan, and P. Chaparala, “Breakdown Walk-in: A New PMOS Failure Mode in High Power BiCMOS Applications,” presented at the IEEE 2003 International Integrated Reliability Workshop, at S. Lake Tahoe, California, on Oct. 22, 2003, and published in the 2003 IEEE International Integrated Reliability Workshop Final Report (Feb. 2004) (four pages).

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