Integrated circuit designing system, method and program

Details Integrated circuit designing system, method and program Integrated circuit designing system, method and program

2007-08-21

2007-08-21

Garbowski, Leigh M. (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000

Reexamination Certificate

active

10972412

ABSTRACT:
When a simulation model generation unit converts logic on the gate level into a basic primitive which can be executed by a simulator to generate a simulation model, for the basic primitives a degeneracy processing unit determines and deletes a gate which can be deleted and which will not affect the delay stage count. The degeneracy processing unit is provided with a constant gate degeneracy unit which puts a plurality of constant gates together, a buffer degeneracy unit which deletes fan-out-free buffers and an identical fan-in gate degeneracy unit which puts identical fan-in gates together.

REFERENCES:
patent: 4602339 (1986-07-01), Aihara et al.
patent: 4816999 (1989-03-01), Berman et al.
patent: 4960724 (1990-10-01), Watanabe et al.
patent: 5210699 (1993-05-01), Harrington
patent: 5463563 (1995-10-01), Bair et al.
patent: 5475605 (1995-12-01), Lin
patent: 5515526 (1996-05-01), Okuno
patent: 6237132 (2001-05-01), Dean et al.
patent: 8-87532 (1996-04-01), None
patent: 2000-353185 (2000-12-01), None

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