Wiring structure for a pad section in a semiconductor device

Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Configuration or pattern of bonds

Reexamination Certificate

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Reexamination Certificate

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11131099

ABSTRACT:
The wiring structure of a pad section in a semiconductor device includes a row of pads and a plurality of first bias wirings provided at either side of the row of pads on a same plane. The first bias wirings carry electrical signals to the pads. A plurality of second bias wirings is formed below the layer having the first bias wirings and the pads. The second bias wirings include a set of wiring parts that run in the direction of the row of pads to overlap with adjacent pads in the layer above. The second bias wirings also include a set of wiring parts that run perpendicular to the direction of the first bias wirings and between two adjacent pads in the layer above.

REFERENCES:
patent: 6785143 (2004-08-01), Nakaoka

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