Probability estimating apparatus and method for peak-to-peak...

Pulse or digital communications – Synchronizers – Phase displacement – slip or jitter correction

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

C375S362000, C375S359000, C375S355000

Reexamination Certificate

active

10082563

ABSTRACT:
A probability estimating apparatus and method for peak-to-peak clock skews for testing the clock skews among a plurality of clock signals distributed by a clock distributing circuit, and for estimating the generation probability of the peak-to-peak value or peak value of the clock skews. The probability estimating apparatus for peak-to-peak values in clock skews includes a clock skew estimator for estimating clock skew sequences among the plurality of clock signals under test and a probability estimator for determining a generation probability of the peak-to-peak values in the clock skews among the plurality of clock signals under test based on the clock skew sequences from the clock skew estimator by applying Rayleigh distribution. The generation probability of the peak-to-peak value is estimated based on RMS values of the clock signals and the Rayleigh distribution.

REFERENCES:
patent: 4542514 (1985-09-01), Watanabe
patent: 4654861 (1987-03-01), Godard
patent: 5402443 (1995-03-01), Wong
patent: 5757652 (1998-05-01), Blazo et al.
patent: 6263034 (2001-07-01), Kanack et al.
patent: 6442214 (2002-08-01), Boleskei et al.
patent: 6640193 (2003-10-01), Kuyel
patent: 6661836 (2003-12-01), Dalal et al.
patent: 6661860 (2003-12-01), Gutnik et al.
patent: 6775321 (2004-08-01), Soma et al.
patent: 6882680 (2005-04-01), Oleynik
patent: 6922452 (2005-07-01), Sandberg
Voorakaranam et al, “Low-Jitter Measurement Technique for Phase-Locked loops”, Circuits and Systems, 2000. Proceedings of the 43rd IEEE Midwest Symposium on, Aug. 2000, vol. 2, pp. 956-959.
Voorakaranam et al “Low-cost Jitter Measurement Technique for Phase-Locked Loop” , (Proceedings of the 43rd IEEE Midwest Symposium on Circuits and Systems, 2000).
Voorakaranam et al “Low-coat Jitter Measurement Technique for Phase-Locked Loop”, Proceedings of the 43rd IEEE Midwest Symposium on Circuits and Systems, vol. 2, Aug. 8-11, 2000 pp. 956-959.
“Jitter Measurement of a PowerPC Microprocessor Using an Analytic Signal Method” IEEE Test Conference, Aug. 8-11, 2000, pp. 956-959.
“Extraction of Peak-to-Peak and RMS Sinusoidal Jitter Using an Analytic Signal Method” 18th TLSI Test Symposium, Apr. 30-May 4, 2000, pp. 395-402.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Probability estimating apparatus and method for peak-to-peak... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Probability estimating apparatus and method for peak-to-peak..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Probability estimating apparatus and method for peak-to-peak... will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-3855216

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.