Processor cache memory as RAM for execution of boot code

Details Processor cache memory as RAM for execution of boot code Processor cache memory as RAM for execution of boot code

2007-08-07

2007-08-07

Padmanabhan, Mano (Department: 2188)

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

Reexamination Certificate

active

10295406

ABSTRACT:
In one embodiment, a computer boot method allows choosing a predetermined data block alignment for a cache that has multiple cross processor interactions. A cache RAM column of a cache as RAM system is loaded with a tag to prevent unintended cache line evictions, and boot code is executed, with the preloaded cache RAM appearing to the executing boot code stream as a memory store.

REFERENCES:
patent: 5809531 (1998-09-01), Brabandt
patent: 6044478 (2000-03-01), Green
patent: 6463509 (2002-10-01), Teoman et al.
patent: 6606686 (2003-08-01), Agarwala et al.
patent: 6842857 (2005-01-01), Lee et al.
patent: 2002/0184352 (2002-12-01), Jain et al.
patent: 1098249 (2001-05-01), None
PCT Search Report, PCT/US03/34808, mailed Feb. 21, 2006.

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