Method of calibrating semiconductor line width

Details Method of calibrating semiconductor line width Method of calibrating semiconductor line width

2007-10-30

2007-10-30

Dinh, Paul (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000

Reexamination Certificate

active

11024755

ABSTRACT:
A method of calibrating a line width in a semiconductor device including fitting line width CD (critical dimension) data to a log function by measuring the line width CD data to plot selectively according to a space size in mask design, fabrication, and correction and applying an output value of the log function as a mask fabrication line width bias by selectively inputting a space value.

REFERENCES:
patent: 2002/0091985 (2002-07-01), Liebmann et al.
patent: 2003/0061595 (2003-03-01), Ki et al.
patent: 2004/0131977 (2004-07-01), Martyniuk et al.
patent: 2004/0212793 (2004-10-01), Koizumi et al.
patent: 1020030039599 (2003-05-01), None

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