Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
2007-11-06
2007-11-06
Thai, Tuan V. (Department: 2186)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
C711S100000, C711S154000
Reexamination Certificate
active
11048350
ABSTRACT:
Techniques for improving cache latency include distributing cache lines across regions of the cache having various latencies. The latencies of the regions may vary as a function of the distance between an individual region of the cache and a cache controller. The cache controller may predict an addressable unit of interest for a next access to a data line stored in a cache line. The predicted addressable unit of interest is stored in a region of the cache having the lowest latency as compared to other regions of the cache. The addressable unit of interest may be a most-recently used addressable unit, an addressable unit sequentially following a most-recently used addressable unit, or determined by other criterion. The invention contemplates using at least one control bit to indicate which addressable unit is stored in the region having the lowest latency.
REFERENCES:
patent: 4424561 (1984-01-01), Stanley et al.
patent: 5091851 (1992-02-01), Shelton et al.
patent: 5732241 (1998-03-01), Chan
patent: 6098152 (2000-08-01), Mounes-Toussi
patent: 6965969 (2005-11-01), Burger et al.
patent: 2005/0223172 (2005-10-01), Bortfeld
patent: 2006/0041720 (2006-02-01), Hu et al.
patent: 2006/0112228 (2006-05-01), Shen
Patterson, David and Hennessy, John. Computer Architecture: A Quantitative Approach, 3rd Ed. Morgan Kaufmann Publishers, 2003. p. 418.
Chishti, Zeshan, et al., “Distance Associativity for High-Performance Energy-Efficient Non-Uniform Cache Architectures,” Proceedings of the 36thInternational Symposium on Microarchitecture (MICRO-36'03); IEEE Computer Society, 2003, 12 pages.
Cragon, Harvey G.,Memory Systems and Pipelined Processors, Jones and Bartlett Publishers, 1996, pp. 15-34 and 91-95.
Kim, Changkyu, et al., “An Adaptive, Non-Uniform Cache Structure for Wire-Delay Dominated On-Chip Caches,” Proceedings of the 10thInternational Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), 2002, pp. 1-12.
Patterson, David A., et al.,Computer Architecture A Quantitative Approach, Morgan Kaufmann Publishers, Inc., 1990, pp. 408-425.
Advanced Micro Devices , Inc.
Thai Tuan V.
Zagorin O'Brien Graham LLP
LandOfFree
Cache word of interest latency organization does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Cache word of interest latency organization, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Cache word of interest latency organization will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3849936