Processor to reduce data rearrangement instructions for...

Details Processor to reduce data rearrangement instructions for... Processor to reduce data rearrangement instructions for...

2007-12-25

2007-12-25

Sparks, Donald (Department: 2187)

Electrical computers and digital processing systems: memory

Addressing combined with specific memory configuration or...

For multiple memory modules

C345S644000

Reexamination Certificate

active

11100490

ABSTRACT:
The present invention provides a processor including: a plurality of memory banks; a read-address generation circuit for supplying a read address to each of the memory banks on the basis of a read-register specification and a read-register scan direction; a read control circuit for executing control to rearrange a plurality of pieces of read data, which is read out from the memory banks in accordance with the read addresses, on the basis of the read-register specification and a read-register displacement; and a processing unit for carrying out a plurality of operations on the rearranged pieces of read data output by the read control circuit.

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“IA-32 Intel (R) Architecture Software Developer's Manual vol. 1: Basic Architecture,” Intel Corporation, 2004.
“AltiVec Technology Programming Interface Manual,,” Motorola Inc., Jun. 1999.

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