Electronic digital logic circuitry – Signal sensitivity or transmission integrity – Output switching noise reduction
Reexamination Certificate
2007-12-25
2007-12-25
Cho, James H. (Department: 2819)
Electronic digital logic circuitry
Signal sensitivity or transmission integrity
Output switching noise reduction
C326S031000, C327S170000
Reexamination Certificate
active
11216199
ABSTRACT:
Various circuit embodiments comprise an input node to receive an input signal for a CMOS transistor stack, a first output node to deliver the input signal to a PMOS pull-up transistor of the CMOS transistor stack, and a second output node to deliver the input signal to an NMOS pull-down transistor of the CMOS transistor stack. A first passive signal path between the input node and the first output node is adapted to pass an effective rising edge of the input signal and delay an effective falling edge of the input signal to a gate of the PMOS transistor. A second passive signal path between the input node and the second output node is adapted to delay the effective rising edge of the input signal and pass the effective falling edge of the input signal to a gate of the NMOS transistor. Other aspects and embodiments are provided herein.
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