Method of protecting a semiconductor integrated circuit from...

Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design

Reexamination Certificate

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C716S030000, C716S030000, C716S030000, C257S355000, C257S356000, C257S491000

Reexamination Certificate

active

10760295

ABSTRACT:
In the design of an integrated circuit having a semiconductor substrate and metal interconnecting lines, including a core ring with metal power and ground lines that supply power to a core area inside the core ring, one or more metal-oxide-semiconductor capacitor units are laid out below the core ring. Each unit has an active area and an insulated gate electrode, which are connected by contacts to the core ring. These capacitor units protect transistors in the core area that have gate electrodes connected to the power or ground line from plasma damage during the fabrication of the integrated circuit. Additional capacitor units laid out below the core ring may be connected to a surrounding input-output ring to protect transistors in input-output circuits, and similar units may be connected to the core ring and input-output ring as protection transistors.

REFERENCES:
patent: 5650651 (1997-07-01), Bui
patent: 5717294 (1998-02-01), Sakai et al.
patent: 5760445 (1998-06-01), Diaz
patent: 5779925 (1998-07-01), Hashimoto et al.
patent: 5828119 (1998-10-01), Katsube
patent: 5955764 (1999-09-01), Katsube
patent: 6028324 (2000-02-01), Su et al.
patent: 6251697 (2001-06-01), Chacon et al.
patent: 6376388 (2002-04-01), Hashimoto et al.
patent: 6389584 (2002-05-01), Kitahara
patent: 6404026 (2002-06-01), Tsuyuki
patent: 6483737 (2002-11-01), Takeuchi et al.
patent: 6496959 (2002-12-01), Noguchi
patent: 6600176 (2003-07-01), Noguchi
patent: 6686254 (2004-02-01), Petrucci et al.
patent: 6884670 (2005-04-01), Hashimoto et al.
patent: 6978437 (2005-12-01), Rittman et al.
patent: 2002/0058390 (2002-05-01), Imai
patent: 2003/0139043 (2003-07-01), Marcus et al.
patent: 2004/0195629 (2004-10-01), Lai et al.
patent: 2005/0227397 (2005-10-01), Kato et al.
patent: 11-168196 (1999-06-01), None
patent: 2004253610 (2004-09-01), None
Kubo et al., : Evaluation of charge build-up in wafer processing by using MOS capacitors with charge collecting electrodes,□□Mar. 22-25, 1995, Microelectronic Test Structures, ICMTS, Proceedings of the International Conference on, pp. 5-9 □□□□.
Shawming et al., “Prediction of plasma charging induced gate oxide damage by plasma charging probe”, May 13-14, 1996, Plasma Process-Induced Damage, 1st International Symposium on, pp. 20-23 □□□□.

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