System and method for applying error correction code (ECC)...

Details System and method for applying error correction code (ECC)... System and method for applying error correction code (ECC)...

2007-12-25

2007-12-25

Chase, Shelly (Department: 2112)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital data error correction

Reexamination Certificate

active

10879643

ABSTRACT:
A system utilizing an erasure mode in an error correction code algorithm is described that includes non-volatile memory storing a page deallocation table. A memory controller stores and retrieves data from a memory subsystem, and uses an error correction code algorithm to correct data corruption in retrieved data. An error analysis algorithm executed in a processor records instances of data corruption in the page deallocation tables and deallocates memory regions associated with multiple occurrences of data corruption at single bit locations. The error analysis algorithm further causes the memory controller to apply an erasure mode of the error correction code algorithm upon detection of a repeated pattern of data corruption across different addresses of the memory subsystem, and removes entries in the page deallocation table that correspond to data corruption addressed by application of the erasure mode.

REFERENCES:
patent: 4475194 (1984-10-01), LaVallee et al.
patent: 7058782 (2006-06-01), Henderson et al.
Chen et al., Fault tolerant memory simulator, Mar. 1984, IMB J. Res. Develop. vol. 28, No. 2, pp. 184-195, retreived from google Feb. 28, 2007.
S. Kaneda and E. Fujiwara; “Single Byte Error Correcting-Double Byte Error Detecting Codes For Memory Systems,” IEEE Transactions on Computers, vol. C-31, No. 7, Jul. 1982.

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