Data processing apparatus and data processing method

Details Data processing apparatus and data processing method Data processing apparatus and data processing method

2007-02-20

2007-02-20

Peugh, Brian R. (Department: 2187)

Electrical computers and digital processing systems: memory

Storage accessing and control

Specific memory composition

C711S165000, C710S260000

Reexamination Certificate

active

10449957

ABSTRACT:
When reading out flash ROM data from an external interface circuit, a clock for a CPU is stopped only in a period during which the flash ROM is read out and fetch data at the CPU side are held in a fetch bus interface; thereafter, an address of the data that are desired to be read out for the flash ROM is output and the data are taken in. When rewriting into the flash ROM, a fetch target from the CPU is switched to a tuning RAM that stores a copy of the data for a rewrite region, and during that period, data rewrite of the flash ROM is carried out. Reading and writing of the flash ROM data from outside is made possible while the CPU is kept in operation.

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patent: 5794054 (1998-08-01), Le et al.
patent: 5951655 (1999-09-01), Inoue
patent: 6782448 (2004-08-01), Goodman et al.
patent: 10-20906 (1998-01-01), None
Russ Hersch, Embedded Processor and Microcontroller primer and FAQ, Sep. 11, 1997, section4.4.
Intel, MCS-51 Microcontroller Family User's Manual, Feb. 1994, Intel Corporation, pp. 2-58, 2-59, 3-28.

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