Semiconductor memory and method of manufacturing the same

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

Reexamination Certificate

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C438S257000, C257S315000, C257SE21179, C257S316000, C257SE21422, C257SE21600

Reexamination Certificate

active

11053952

ABSTRACT:
A semiconductor memory has plural cell transistors that are arranged in a matrix. The cell transistor comprises a silicon substrate, a control gate, a pair of electrically isolated floating gates. Plural projections are formed in the P type silicon substrate, and a pair of N type diffusion regions as the source and the drain is formed in both sides of the projection. The control gate faces the projection via a fourth insulation layer. The side surface of the floating gates faces the side surfaces of the projection via a first insulation layer, and faces the control gate via a third insulation layer. The floating gate faces the diffusion region via the first insulation layer.

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patent: 6538925 (2003-03-01), Miida
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patent: 2004/0169219 (2004-09-01), Miida et al.
patent: 2006/0108630 (2006-05-01), Miida

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