Register renaming for dynamic multi-threading

Details Register renaming for dynamic multi-threading Register renaming for dynamic multi-threading

2007-12-25

2007-12-25

Chan, Eddie (Department: 2183)

Electrical computers and digital processing systems: processing

Dynamic instruction dependency checking, monitoring or...

Scoreboarding, reservation station, or aliasing

Reexamination Certificate

active

10184250

ABSTRACT:
A register renaming technique for dynamic multithreading. One disclosed embodiment includes a register map to store up to M×N values to map M registers for N threads. A set of N values, one per thread, and a set of state bits is associated with each of the M registers. Each set of state bits indicates which of the N values per register are valid and whether ones of the N sets of values have been written by a dynamic execution thread. In response to termination of a dynamic execution thread, recovery logic may update state bits associated with ones of the M registers that were written to during dynamic execution.

REFERENCES:
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Y. Chou, J. Fung, and J. Shen, “Reducing Branch Misprediction Penalites via Dynamic Control and Independence Detection,” Int'l Conference on Super-computing, Jun. 1999, 19 pages.
A. Klauser, A. Paithankar, and D. Grunwald, “Selective Eager Execution on the Polypath Architecture,” 25thInt'l Symposium on Computer Architecture, Jun. 1998, 10 pages.

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