Method of comparison between cache and data register for...

Details Method of comparison between cache and data register for... Method of comparison between cache and data register for...

2007-08-07

2007-08-07

Phan, Trong (Department: 2827)

Static information storage and retrieval

Associative memories

Ferroelectric cell

C365S189070, C365S189080

Reexamination Certificate

active

11580660

ABSTRACT:
A non-volatile memory device and data comparison circuit are described that facilitate the comparison of data between two blocks of data, such as the I/O buffer or data cache of a memory and the sense amplifiers, that allow for simple and rapid comparison of data bits and results in a signal flag indicating a data match or a mis-match. This allows for a simple parallel data bit comparison capability that allows a fast initial comparison result without requiring a time-consuming individual bit-by-bit data comparison. In one embodiment, two data blocks to be compared are divided into a number of paired segments, wherein each pair of segments are compared in parallel by a data comparison circuit, such that a mis-match can be located to the affected data segments or the results logically combined to indicate a match or mis-match for the complete data blocks.

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