Power/performance optimized cache using memory write...

Details Power/performance optimized cache using memory write... Power/performance optimized cache using memory write...

2007-06-19

2007-06-19

Peikari, B. James (Department: 2189)

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

C711S142000, C711S141000, C711S144000, C711S145000

Reexamination Certificate

active

10335131

ABSTRACT:
A multiprocessor system may include multiple processors and multiple caches associated with the processors. The system may employ a memory snarfing technique to reduce writes to the system (or main) memory. Cache-ownership capable agents, e.g., agents with write-back caches, may snarf the data (obtain the cache line) if the required cache line is in a valid state in the agent's cache.

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