Method and apparatus to counter mismatched burst lengths

Details Method and apparatus to counter mismatched burst lengths Method and apparatus to counter mismatched burst lengths

2007-10-09

2007-10-09

Bataille, Pierre-Michel (Department: 2186)

Electrical computers and digital processing systems: memory

Addressing combined with specific memory configuration or...

For multiple memory modules

C711S154000

Reexamination Certificate

active

10750154

ABSTRACT:
Memory device having banks of memory cells organized into two groups of banks that share control circuitry and a data buffer to provide an interface to a memory bus, but which are independently operable enough to support unrelated transactions with each group, and can be used to stagger read operations with shortened burst transfers so as to minimize dead time on a memory bus.

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IBM Technical Disclosure Bulletin, “Bit Vector Algortihm for Detecting Self-Modification in Data Chains”, Oct. 1, 1989, vol. 32, Issue 5A, pp. 455-457 (5 pages included in printout).
Saulsbury, A., et al., “Missing th Memory Wall: The Case for Processor/Memory Integration”, Proceedings of the 23rd Annual Intl. Symposium on Computer Architecture, vol. 24(2):90-101 (May 1996).

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