Non-volatile memory structure

Details Non-volatile memory structure Non-volatile memory structure

2007-02-27

2007-02-27

Booth, Richard A. (Department: 2812)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C438S258000, C257SE27103

Reexamination Certificate

active

11308621

ABSTRACT:
A non-volatile memory structure including a substrate, a first memory cell row, a first source/drain region, and a second source/drain region is described. The first memory cell row is disposed on the substrate and includes a plurality of memory cells, two select gate structures, and a plurality of doped regions. The select gate structures are respectively disposed on the substrate at one side of the outmost memory cell among the memory cells, and the select gates have a tapered corner at one side far from the memory cells. The doped regions are respectively disposed in the substrate between two memory cells as well as in the substrate between the memory cells and the select gate structures. The first and the second source/drain regions are respectively disposed in the substrate at both sides of the first memory cell row.

REFERENCES:
patent: 6218689 (2001-04-01), Chang et al.
patent: 2002/0098651 (2002-07-01), Yim et al.
patent: 2005/0035396 (2005-02-01), Yaegashi
patent: 2006/0040447 (2006-02-01), Violette et al.

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