Semiconductor memory devices having negatively biased sub...

Details Semiconductor memory devices having negatively biased sub... Semiconductor memory devices having negatively biased sub...

2007-07-24

2007-07-24

Phan, Trong (Department: 2827)

Static information storage and retrieval

Addressing

Plural blocks or banks

C365S230060, C365S189110

Reexamination Certificate

active

11344018

ABSTRACT:
Semiconductor memory devices having a negatively biased sub-word line scheme and methods of driving the same are disclosed. In a semiconductor memory device, NMOS transistors for pulling down a word line enable signal and a word line driving signal to a negative voltage are adjusted to a negative voltage. The negatively biased word line scheme may decrease influx of discharge current into the negative voltage source and decrease negative voltage fluctuations and associated noise.

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