Method of floorplanning and cell placement for integrated...

Details Method of floorplanning and cell placement for integrated... Method of floorplanning and cell placement for integrated...

2007-02-06

2007-02-06

Whitmore, Stacy A (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

Reexamination Certificate

active

10947618

ABSTRACT:
A method and computer program are disclosed for floorplanning and cell placement of an integrated circuit architecture that include steps of: (a) receiving as input a design for an integrated circuit architecture that includes a plurality of modules and an internal I/O ring; (b) creating a floorplan to define an area for placing module cells for each module in the plurality of modules wherein for each module that overlaps the internal I/O ring, an area of intersection between the area defined for placing the module cells and an area bounded by a side of the internal I/O ring for which the area of intersection is least is a global minimum for the plurality of modules; and (c) generating as output the floorplan for the integrated circuit architecture.

REFERENCES:
patent: 6057109 (2000-05-01), Tartaglia
patent: 6457157 (2002-09-01), Singh et al.
patent: 6823501 (2004-11-01), Dahl
patent: 6829754 (2004-12-01), Yu et al.
patent: 2006/0064660 (2006-03-01), Chung-Maloney et al.

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