Charge trapping memory cell and fabrication method

Details Charge trapping memory cell and fabrication method Charge trapping memory cell and fabrication method

2007-06-05

2007-06-05

Andujar, Leonardo (Department: 2826)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S319000, C257S329000, C257S330000, C257S316000, C257S335000, C257S295000, C257S298000, C257S314000, C257S315000

Reexamination Certificate

active

11055584

ABSTRACT:
A memory cell patterned as a trench transistor is provided with a first gate electrode (4) as auxiliary gate for source-side injection and a second gate electrode (5) electrically insulated therefrom, which are arranged in the trench, and has, at the trench walls, a storage layer sequence (10) provided for charge trapping and comprising a storage layer (12) between boundary layers (11, 13). The first gate electrode (4) and the second gate electrode (5) are electrically insulated from one another, which can be effected by means of a portion of the storage layer sequence (10). Source/drain regions (3) are arranged on the top side laterally with respect to the trenches. Word lines (6), source/drain lines and control gate lines are present for the electrical driving.

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