Static information storage and retrieval – Addressing – Sync/clocking
Reexamination Certificate
2007-01-30
2007-01-30
Phung, Anh (Department: 2824)
Static information storage and retrieval
Addressing
Sync/clocking
C365S222000, C365S191000
Reexamination Certificate
active
10894823
ABSTRACT:
The present invention relates to a synchronous semiconductor memory device with double data rate, and more particularly, to a synchronous semiconductor memory device for inputting and outputting data using a free-running clock and inserting a preamble indicative of start of data into the outputted data. A semiconductor memory device of the present invention receives a data read command from the exterior of the memory device in response to a predetermined clock signal inputted from the exterior, and outputting data including a preamble in response to the clock signal.
REFERENCES:
patent: 6151270 (2000-11-01), Jeong
patent: 6198674 (2001-03-01), Kim
patent: 6222792 (2001-04-01), Hanzawa et al.
patent: 6807613 (2004-10-01), Keeth et al.
patent: 2003/0218916 (2003-11-01), Kang
Mills & Onello LLP
Nguyen Dang
Phung Anh
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