Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2007-11-20
2007-11-20
Do, Thuan (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000, C703S014000
Reexamination Certificate
active
11105611
ABSTRACT:
A method, system and computer program product for preserving constraints is disclosed. The method comprises receiving an initial design including one or more targets, one or more primary inputs, one or more constraints and one or more state elements. A cut of the initial design including one or more cut gates, and a relation of one or more values producible to the one or more cut gates in terms of the one or more primary inputs and the one or more state elements is computed. The relation is constrained to force one or more constraint gates representing the one or more constraints to evaluate to a forced valuation, and one or more dead-end states of the constraints are identified. The inverse of the dead-end states is applied as don't cares to simplify the relation and the simplified relation is synthesized to form a first gate set. An abstracted design is from the first gate set and verification is performed on the abstracted design to generate verification results.
REFERENCES:
patent: 6823500 (2004-11-01), Ganesh et al.
Kukula et al., Computer Aided Verification, 12thInternational Conference on Computer Aided Verification, Jul. 15-19, 2000.
Moon et al., Simplifying Circuits for Formal Verification Using Parametric Representation, Formal Methods in Computer-Aided Design, 2002, pp. 52-69.
Yuan et al., Constraint Synthesis for Environment Modeling in Functional Verification, Design Automation Conference, Jun. 2-6, 2003.
Baumgartner Jason Raymond
Janssen Geert
Mony Hari
Paruthi Viresh
Dillon & Yudell LLP
Do Thuan
Salys Casimer K.
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