Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2007-11-27
2007-11-27
Garbowski, Leigh M. (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000
Reexamination Certificate
active
10962672
ABSTRACT:
An apparatus for designing a layout includes an arranging unit that arranges, on a large-scale-integrated chip, a cell in which a signal line segment that is not connected to a terminal is formed; a wiring unit that wires a signal line to an arbitrary wiring layer of the large-scale-integrated chip; and a connecting unit that connects the signal line segment with the signal line.
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“Fujitsu Releases AccelArray™ Structured ASIC Devices,”FUJITSU, Jun. 26, 2003.
Abe Koji
Kondo Eiji
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