Method for testing semiconductor memory modules

Details Method for testing semiconductor memory modules Method for testing semiconductor memory modules

2007-11-13

2007-11-13

Kerveros, James C. (Department: 2138)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Memory testing

C714S719000

Reexamination Certificate

active

10126376

ABSTRACT:
A method for testing semiconductor memory modules in which data are stored in banks with an addressable matrix structure containing rows and columns. Defect addresses of the defect locations in the banks are transmitted in compressed form to an external test device. The rows and/or the columns are subdivided into regions. The defects occurring in the respective region are counted row by row and/or column by column. The number of defects in each region is compared row by row and/or column by column with a threshold value, and the comparison results are transmitted as additional information row by row and/or column by column together with the defect addresses to a test device.

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