Method and structure for tungsten gate metal surface...

Details Method and structure for tungsten gate metal surface... Method and structure for tungsten gate metal surface...

2007-03-06

2007-03-06

Pizarro-Crespo, Marcos D. (Department: 2814)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

Insulated gate formation

C438S592000, C438S508000

Reexamination Certificate

active

10862990

ABSTRACT:
As disclosed herein, an FEOL line conductor stack is formed including a base conductor layer, an overlying layer of tungsten, and an optional gate capping layer. The stack, including layers from the optional capping layer down to the base conductor layer are directionally etched until an underlying layer is exposed. Then, the substrate is exposed to one or the other or both of: 1) a silicon-containing ambient to form a self-aligned layer of tungsten silicide on sidewalls of the tungsten layer; and 2) a source of nitrogen to form a thin layer of tungsten nitride on sidewalls of the tungsten layer. Such tungsten silicide and/or tungsten nitride layers serves to protect the tungsten during subsequent processing, among which may include sidewall oxidation (e.g. for a polysilicon base conductor layer) and/or the forming of silicon nitride spacers on sidewalls of the gate stack.

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