Control of wafer warpage during backend processing

Details Control of wafer warpage during backend processing Control of wafer warpage during backend processing

2007-07-24

2007-07-24

Smith, Zandra V. (Department: 2822)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S636000, C438S671000, C257S758000, C257S760000, C257S773000

Reexamination Certificate

active

11068237

ABSTRACT:
A method of fabricating an integrated circuit (IC), during which wafer warpage is controlled by appropriately controlling intrinsic stresses in one or more service layers of the layer stack of the IC's multilevel interconnect structure. In one embodiment, each interconnect level of the multilevel interconnect structure has a dielectric layer, a conducting layer formed over the dielectric layer, and a service anti-reflective coating (ARC) layer formed over the conducting layer. Each ARC layer is formed from silicon oxynitride such that at least two ARC layers corresponding to different interconnect levels have different intrinsic stresses. The amount of intrinsic stress in each ARC layer is controlled, e.g., through the control of temperature and/or gas composition during the layer deposition.

REFERENCES:
patent: 6432845 (2002-08-01), Morozumi
patent: 6867129 (2005-03-01), Tu
patent: 7008869 (2006-03-01), Han
patent: 7057262 (2006-06-01), Goldstein
“Silicon Nitride and Oxynitride Films,” by F. H. P. M. Habraken and A. E. T. Kuiper, Mater. Sci. Eng. R12, No. 3, (1994) pp. 123-175.
“Characterization of PECVD Deposited Silicon Oxynitride Thin Films,” by S. P. Speakman, et al, Vacuum, v. 38, No. 3, (1988) pp. 183-188.

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