Method and apparatus for high throughput short packet...

Details Method and apparatus for high throughput short packet... Method and apparatus for high throughput short packet...

2007-09-04

2007-09-04

Park, Ilwoo (Department: 2182)

Electrical computers and digital data processing systems: input/

Input/output data processing

Input/output data buffering

C710S054000, C710S056000

Reexamination Certificate

active

10698154

ABSTRACT:
A device is presented including a host controller. A host controller driver is connected to the host controller. The host controller arranges queue element transfer descriptors (qTDs) in a circularly linked order. Also presented is a method including determining whether execution of a first queue element transfer descriptor (qTD) in a first bank including many qTDs results in a short packet condition. Following an alternate pointer in the first bank that points to a second bank if execution of the first qTD resulted in the short packet condition. Following a next pointer to a second qTD in the first bank if the execution of the first qTD completed normally. Also executing the second qTD in the first bank. The qTDs in the first bank and the second bank are circularly linked.

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“Enhanced Host Controller Interface Specification for Universal Serial Bus”, Pub. date Jun. 20, 2001, Revision 0.96.

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