Semiconductor device manufacturing: process – Coating of substrate containing semiconductor region or of...
Reexamination Certificate
2007-05-22
2007-05-22
Lindsay, Jr., Walter (Department: 2812)
Semiconductor device manufacturing: process
Coating of substrate containing semiconductor region or of...
C257SE31041
Reexamination Certificate
active
11049671
ABSTRACT:
A semiconductor device including a gate insulating film selectively formed on a predetermined region of a semiconductor substrate; a gate electrode formed on said gate insulating film; and a source region and drain region formed, in a surface portion of said semiconductor substrate, on two sides of a channel region positioned below said gate electrode; wherein a carbon concentration in an interface where said gate insulating film is in contact with said gate electrode is not more than 5×1022atoms/cm3.
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Katsuyuki Sekine, et al.; “Nitrogen Profile Control by Plasma Nitridation Technique for Poly-Si Gate HfSiON CMOSFET with Excellent Interface Property and Ultra-low Leakage Current”; 2003 IEDM, Dig. Tech. Papers, pp. 103-106; (2003).
Notification of Reason for Rejection issued by the Japanese Patent Office on Feb. 6, 2007, for Japanese Patent Application No. 2004-317773, and English-language translation thereof.
Eguchi Kazuhiro
Inumiya Seiji
Kaneko Akio
Sato Motoyuki
Sekine Katsuyuki
Finnegan Henderson Farabow Garrett & Dunner L.L.P.
Kabushiki Kaisha Toshiba
Lindsay, Jr. Walter
Ullah Elias
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