Digital system having selectable clock speed based upon...

Details Digital system having selectable clock speed based upon... Digital system having selectable clock speed based upon...

2007-05-15

2007-05-15

Cao, Chun (Department: 2115)

Electrical computers and digital processing systems: support

Computer power control

Power conservation

C713S600000

Reexamination Certificate

active

10986254

ABSTRACT:
Clock speed is controlled based upon the supply voltage to a digital device. When the supply voltage is below a reference voltage the clock speed will be slower than if the supply voltage is above the reference voltage. A phase-lock-loop (PLL) may be used to generate a higher frequency that is an integer multiple of a reference oscillator. The clock speed will be proportional to the frequency multiplication of the PLL when the faster clock speed is selected. A multiplexer is used to switch between different frequency sources, and a timer can be used to insure stable operation of the PLL. A status configuration register has status and control bits for indicating and controlling operation of the clock speed control. A universal serial bus (USB) device can operate at a slower clock with reduced operating voltage, and at a faster clock with increased operating voltage.

REFERENCES:
patent: 6515530 (2003-02-01), Boerstler et al.
patent: 6828848 (2004-12-01), Lee
patent: 2004/0017234 (2004-01-01), Tam et al.
patent: 2004/0057324 (2004-03-01), Abe et al.
patent: 10063147 (2000-12-01), None
patent: 0704976 (1996-04-01), None
patent: 1306740 (2003-05-01), None
PCT International Search Report and Written Opinion; PCT/US2005/018646; 13 Pgs.

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