Phase locked loop circuit and clock reproduction circuit

Pulse or digital communications – Synchronizers – Phase displacement – slip or jitter correction

Reexamination Certificate

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Details

C375S373000, C375S375000, C327S156000, C327S147000

Reexamination Certificate

active

10300745

ABSTRACT:
A phase locked loop circuit and a clock reproduction circuit can operate stably with satisfying both of wide lock range and good jitter characteristics. The phase locked loop circuit for generating a clock signal in synchronized in phase with an input signal, has a phase comparator having an analog characteristics as a phase difference detection output characteristics and detecting a phase difference between the input signal and the clock signal, a first control loop controlled oscillation depending upon the phase difference detection output and a second control loop controlled oscillation depending upon a signal derived from the phase difference detection output with enhancing frequency components near a direct current component and performs low speed control in comparison with the first control loop.

REFERENCES:
patent: 4580107 (1986-04-01), Caldwell et al.
patent: 5012494 (1991-04-01), Lai et al.
patent: 5142246 (1992-08-01), Petersson
patent: 5836000 (1998-11-01), Choi
patent: 6147530 (2000-11-01), Nogawa
patent: 6271731 (2001-08-01), Koszarsky
patent: 6353647 (2002-03-01), Wilhelmsson et al.
patent: 6643346 (2003-11-01), Pedrotti et al.

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