Electrical computers and digital processing systems: memory – Storage accessing and control – Specific memory composition
Reexamination Certificate
2007-09-25
2007-09-25
Elmore, Reba I. (Department: 2189)
Electrical computers and digital processing systems: memory
Storage accessing and control
Specific memory composition
C711S154000, C711S166000
Reexamination Certificate
active
10886063
ABSTRACT:
A scrubbing controller used with a DRAM stores data in an error correcting code format. The system then uses a memory control state machine and associated timer to periodically cause the DRAM to read the error correcting codes. An ECC generator/checker in the scrubbing controller then detects any errors in the read error correcting codes, and generates corrected error correcting codes that are written to the DRAM. This scrubbing procedure, by reading error correcting codes from the DRAM, inherently refreshes memory cells in the DRAM. The error correcting codes are read at rate that may allow data errors to be generated, but these errors are corrected in the memory scrubbing procedure. However, the low rate at which the error correcting codes are read results in a substantial power saving compared to refreshing the memory cells at a higher rate needed to ensure that no data errors are generated.
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Stallings, William, “Computer Organization&Architecture: Designing for Performing,” pp. 103-116.
Dorsey & Whitney LLP
Elmore Reba I.
Micro)n Technology, Inc.
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