Apparatus and method for transmitting/receiving error...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction

Reexamination Certificate

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C714S715000, C714S781000

Reexamination Certificate

active

10742684

ABSTRACT:
Disclosed is an apparatus for generating an error detection information bit sequence for determining a length of data sequence transmitted in a communication system. The apparatus comprises a plurality of cascaded registers, the number of which is identical to the number of bits in the error detection information bit sequence, and a plurality of adders arranged on paths determined by a predetermined generator polynomial, each of the adders adding a bit sequence received through an input path to a feedback bit sequence. During reception of the control information sequence, an operator generates the feedback bit sequence by sequentially adding bits of the control information sequence to output bits of a final register and provides the generated feedback bit sequence to the adders. After completion of receiving the control information sequence, the operator sequentially adds a preset input bit to output bits of the final register and outputs the addition result as the error detection information bit sequence. An initial value controller provides the registers with a selected initial value separately determined for the data sequences.

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patent: 4972436 (1990-11-01), Halim et al.
patent: 5862160 (1999-01-01), Irvin et al.
patent: 6233251 (2001-05-01), Kurobe et al.
patent: 6374383 (2002-04-01), Weng
patent: 6983414 (2006-01-01), Duschatko et al.
patent: 2003/0053435 (2003-03-01), Sindhushayana et al.
patent: 03/226019 (1991-10-01), None
patent: 11/136138 (1999-05-01), None
patent: WO 99/41853 (1999-08-01), None

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