Full wafer silicon probe card for burn-in and testing and...

Metal working – Method of mechanical manufacture – Electrical device making

Reexamination Certificate

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C324S765010

Reexamination Certificate

active

10454969

ABSTRACT:
A full-wafer probe card is disclosed along with related methods and systems. The probe card includes test probes comprising cantilever elements configured and arranged with probe tips in a pattern corresponding to an array of bond pads of semiconductor dice residing on a device wafer. The probe card may be fabricated from, for example, a silicon substrate and the cantilever elements may be fabricated using known silicon micro-machining techniques including isotropic and anisotropic etching. Additionally, conductive feedthroughs or vias are formed through the probe card to electrically connect the probe tips with conductive pads on an opposing side of the substrate which interface with test contacts of external test circuitry. The conductive feedthroughs may be formed as coaxial structures, which help to minimize stray capacitance and inductance. The inventive probe card allows for improved wafer level burn-in and high frequency testing.

REFERENCES:
patent: 5268571 (1993-12-01), Yamamoto et al.
patent: 5475318 (1995-12-01), Marcus et al.
patent: 5623214 (1997-04-01), Pasiecznik, Jr.
patent: 5642054 (1997-06-01), Pasiecznik, Jr.
patent: 5773780 (1998-06-01), Eldridge et al.
patent: 5806181 (1998-09-01), Khandros et al.
patent: 5829128 (1998-11-01), Eldridge et al.
patent: 6060891 (2000-05-01), Hembree et al.
patent: 6072321 (2000-06-01), Akram et al.
patent: 6100708 (2000-08-01), Mizuta
patent: 6143616 (2000-11-01), Geusic et al.
patent: 6181144 (2001-01-01), Hembree et al.
patent: 6187677 (2001-02-01), Ahn
patent: 6379982 (2002-04-01), Ahn et al.
patent: 6531327 (2003-03-01), Kanamaru et al.
FormFactor WOWs wieth Cost Savings, Electronic Buyers' News (EBUY), Copyright 1998 CMP Publications Inc., Dec. 14, 1998, pp. 7-9.
Beiley et al., A Mircomachined Array Probe Card -Fabrication Process, IEEE Transactions on Components Packaging and Manufacturing Technology, Feb. 1995, Part B, vol. 12, No. 1, pp. 179-182.
Arnold et al., Test Methods Used to Produce Highly Reliable Known Good Die (KGD), 1998 International Conference on Multichip Modules and Hight Density packaging, Dallas, TX, pp. 374-392.
Zhang et al., A New MEMS Wafer Probe Card, Newark, NJ, pp. 395-399.
Smith et all, A New Flip-Chip Technology for High-Density packaging, 1196 Electronic Components and Technology Conference, pp. 1069-1073.
Jazairy et al., Very High Aspect Ratio Wafer-Free Silicon Micromechanical Structures, School of Electrical Engineering and the National Nanofabrication Facility, Cornell University, Ithaca, NY, SPIE vol. 2640, pp. 111-120.
Kasukabe et al., Membrane Probe with Pryamidal Tips for a Bare Chip Testing, 1998 International Conference on Multichip Modules and High Density Packaging, pp. 383-387.
Criscuolo, Using Silicon Contacts to Test and Buro-in Flash Memory, Microprocessors, and FPGA's, 1998 International Conference on Multichip Modules and High Density Packaging, pp. 388-392.

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