Method and apparatus for implementing frame header alterations

Details Method and apparatus for implementing frame header alterations Method and apparatus for implementing frame header alterations

2007-05-15

2007-05-15

Nguyen, Hanh (Department: 2616)

Multiplex communications

Communication techniques for information carried in plural...

Adaptive

C370S412000, C370S389000, C370S503000

Reexamination Certificate

active

10185552

ABSTRACT:
A method and apparatus are provided for implementing frame header alterations in a network processor. A command decoder receives and decodes frame alteration commands and provides frame alignment commands and alteration instructions. A data aligner receives frame data and is coupled to the command decoder receiving the frame alignment commands. The data aligner includes an insert and delete unit that sequentially receives a predefined number of bytes of frame data, selectively latches data bytes of the received predefined number of bytes of frame data responsive to the frame alignment commands and sequentially provides an aligned frame data output of the predefined number of bytes. An alteration engine is coupled to the data aligner receiving the sequential aligned frame data output and is coupled to the command decoder receiving the alteration instructions. The alteration engine provides sequential altered frame data responsive to the received alteration instructions.

REFERENCES:
patent: 5168561 (1992-12-01), Vo
patent: 5857113 (1999-01-01), Muegge et al.
patent: 6731652 (2004-05-01), Ramfelt et al.
patent: 7000097 (2006-02-01), Senter et al.
U.S. Appl. No. 180,993, filed Jun. 27, 2002, entitled “Method and Apparatus for Implementing Alterations on Multiple Concurrent Frames”.
U.S. Appl. No. 185,556, filed Jun. 27, 2002, entitled “Method and Apparatus for Implementing Frame Header Alterations Using Byte-Wise Arithmetic Logic Units”.

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