Method for forming 1 TRAM cell and structure formed thereby

Details Method for forming 1 TRAM cell and structure formed thereby Method for forming 1 TRAM cell and structure formed thereby

2007-07-24

2007-07-24

Pham, Long (Department: 2814)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S311000

Reexamination Certificate

active

10827389

ABSTRACT:
A single transistor random access memory cell has an MOS well, a transfer gate of the transistor and a storage capacitor having a storage node in the well that becomes an inversion layer at a threshold voltage near zero. The inversion layer diffuses to an inversion region beneath the transfer gate when the transfer gate is turned on. For high speed operation, a doped region beneath the transfer gate becomes an inversion layer at a threshold voltage near zero. In this invention, a storage node junction is removed, which removes junction leakage and reduces subthreshold leakage current significantly.

REFERENCES:
patent: 2002/0163848 (2002-11-01), Grasso
patent: 2003/0095427 (2003-05-01), Afghahi et al.
patent: 2004/0043587 (2004-03-01), Lawlor

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