Memory

Details Memory Memory

2007-07-17

2007-07-17

Phung, Anh (Department: 2824)

Static information storage and retrieval

Read/write circuit

Data refresh

C365S194000

Reexamination Certificate

active

11228215

ABSTRACT:
A memory capable of performing a refresh operation without increasing current consumption is provided. This memory comprises a plurality of memory cells storing data, a delay circuit outputting a first address signal corresponding to the memory cells received from outside for a normal access operation with a delay of a prescribed period, a refresh control circuit outputting a second address signal corresponding to any of the memory cells subjected to a refresh operation of the data and a switching circuit switching and outputting the first address signal output from the delay circuit and the second address signal output from the refresh control circuit.

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Office Action for Corresponding Application No. 10-2005-88546, Dispatch Date: Jul. 27, 2006.

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