Electronic apparatus and method for controlling...

Electrical computers and digital processing systems: support – Computer power control – Power conservation

Reexamination Certificate

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C713S324000, C365S229000

Reexamination Certificate

active

10822838

ABSTRACT:
When an event takes place in a standby mode, data corresponding to the event is set to a shadow register. The shadow register is operated with a low speed local clock. The contents of the shadow register are copied to a bus IF register through a selector. The bus IF register is connected to a main circuit through a system LSI bus. Data is read from/written to the bus IF register in synchronization with a high speed clock. When the status of the bus IF register changes, a CPU is notified of an interrupt. In a normal mode, an event corresponding to a status change is set to the data bus IF register not through the shadow register. In the standby mode, power of the main circuit is turned off. The high speed clock for the bus IF register is stopped. Thus, the power consumption can be reduced.

REFERENCES:
patent: 6578137 (2003-06-01), Parady
patent: 6664148 (2003-12-01), Goto et al.
patent: 6879196 (2005-04-01), Lutkemeyer
patent: 6914845 (2005-07-01), Ooishi
patent: 10333881 (1998-12-01), None

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