Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2007-07-03
2007-07-03
Chiang, Jack (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000
Reexamination Certificate
active
10989679
ABSTRACT:
A method of implementing a design on a programmable logic device (PLD) includes generating a database that identifies correspondence between resources and programming frames of the PLD. A first PLD design is compiled, wherein the first design uses a first set of resources in a first manner. Costs associated with using the first set of resources of the first design in the first manner are reduced. A second PLD design is then compiled, applying the reduced costs associated with using the first set of resources. A second set of resources required to compile the second design is identified, wherein the second set of resources is not used in the same manner as the first set of resources. A set of programming frames associated with the second set of resources is identified. Costs associated with using a third set of resources associated with the set of programming frames are increased.
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patent: 7024651 (2006-04-01), Camilleri et al.
patent: 7073158 (2006-07-01), McCubbrey
U.S. Appl. No. 10/966,643, filed Oct. 15, 2004, Young et al.
Lesea Austin H.
New Bernard J.
Trimberger Stephen M.
Chiang Jack
Cuenot Kevin T.
Hardaway Michael R.
Hoffman E. Eric
Tat Binh
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