Method and system for reducing the peak current in...

Details Method and system for reducing the peak current in... Method and system for reducing the peak current in...

2007-04-03

2007-04-03

Nguyen, Viet Q. (Department: 2827)

Static information storage and retrieval

Read/write circuit

Data refresh

C365S233100, C365S194000, C365S230030

Reexamination Certificate

active

10931564

ABSTRACT:
A dynamic random access memory device includes a mode register that is programmed with a delay value. In some embodiments, a offset code is also stored in the memory device. The memory device uses the delay value, which may be added to or multiplied by the offset code, to delay the initiation of a received auto-refresh or self-refresh command. A large number of dynamic random access memory devices in a system may be provided with different delay values and possibly offset codes so that the memory device do not all perform refreshes simultaneously in response to an auto-refresh or self-refresh command issued to all of the memory devices simultaneously. As a result, the peak current drawn by the memory devices resulting from the auto-refresh command or self-refresh command is maintained at a relatively low value.

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patent: 6842864 (2005-01-01), Barth et al.
patent: 7043599 (2006-05-01), Ware et al.
patent: 2003/0227801 (2003-12-01), Battaglia

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