Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
Reexamination Certificate
2007-05-01
2007-05-01
Baker, Stephen M. (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital data error correction
C714S765000
Reexamination Certificate
active
10950738
ABSTRACT:
A system for securely storing data in a memory includes a memory (1) and a CPU (Central Processing Unit) (2). The memory is divided into a plurality of fixed-size blocks (10) for storing data. Each block includes a plurality of data pages (101), and a parity check page (102) storing check codes for checking and recovering byte data. Each data page includes a plurality of byte addresses for storing byte data including a CRC (Cyclic Redundancy Check), and a complement of the CRC in the hexadecimal system expressed as CRC′. The CPU is for calculating a CRC for each data page according to byte data of the data page, calculating a CRC′ based on the CRC of the data page, and for identifying and correcting any incorrect bit data. A related method is also disclosed.
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Baker Stephen M.
Hon Hai Precision Industry Co. Ltd.
Morris Manning & Martin LLP
Tingkang Xia, Esq. Tim
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