Method and apparatus for a calibrated variable phase offset...

Details Method and apparatus for a calibrated variable phase offset... Method and apparatus for a calibrated variable phase offset...

2007-01-23

2007-01-23

Nguyen, Hiep T. (Department: 2187)

Electrical computers and digital processing systems: memory

Storage accessing and control

Access timing

C711S105000, C713S401000, C713S500000

Reexamination Certificate

active

10919668

ABSTRACT:
A method and apparatus for a calibrated variable phase offset timing between synchronous clock subdomains is described. In one embodiment, the invention is an apparatus. The apparatus includes a first subsystem and a second subsystem coupled to the first subsystem. The apparatus also includes a clock signal generator coupled to the first subsystem and coupled to the second subsystem. The clock signal generator is to supply a first clock to the first subsystem and to supply a second clock to the first subsystem and to supply a third clock to the second subsystem. Each of the first clock, the second clock and the third clock are derived from a common clock, the first clock having a first predetermined phase offset relative to the third clock, and the second clock having a second predetermined phase offset relative to the third clock. The first predetermined phase offset and the second predetermined phase offset are adjustable based on performance characteristics of the first subsystem and performance characteristics of the second subsystem.

REFERENCES:
patent: 3633174 (1972-01-01), Griffon
patent: 6026050 (2000-02-01), Baker et al.
patent: 6334174 (2001-12-01), Delp et al.
patent: 6553472 (2003-04-01), Yang et al.
patent: 6646953 (2003-11-01), Stark
patent: 6779096 (2004-08-01), Cornelius et al.
patent: 2003/0084233 (2003-05-01), Willams

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