System and method for verifying HDL events for observability

Details System and method for verifying HDL events for observability System and method for verifying HDL events for observability

2007-04-03

2007-04-03

Baderman, Scott (Department: 2114)

Error detection/correction and fault detection/recovery

Data processing system error or fault handling

Reliability and availability

C702S058000, C702S059000

Reexamination Certificate

active

10402122

ABSTRACT:
In one embodiment, the invention is directed to a method of verifying conditions occurring during a simulation of a hardware design. The method comprises logging each occurrence of at least one specified condition in a first log; logging signals observed at an observability port in a second log; and comparing the first and second logs to determine whether for each occurrence of the at least one specified condition logged in the first log, a corresponding entry identifying a signal expected to be observed responsive to occurrence of the at least one specified condition is logged in the second log.

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Bart Vermeulen and Sandeep Kumar Goel, “Design for Debug: Catching Design Errors in Digital Chips”, IEEE Design & Test of Computers; May-Jun. 2002; pp. 37-45.

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