Electrical computers and digital processing systems: memory – Storage accessing and control – Access timing
Reexamination Certificate
2007-01-02
2007-01-02
Portka, Gary (Department: 2188)
Electrical computers and digital processing systems: memory
Storage accessing and control
Access timing
C713S400000, C713S503000
Reexamination Certificate
active
10686118
ABSTRACT:
A method and circuit adaptively adjust respective timing offsets of digital signals relative to a clock output along with the digital signals to enable a latch receiving the digital signals to store the signals responsive to the clock. A phase command for each digital signal is stored in an associated storage circuit and defines a timing offset between the corresponding digital signal and the clock. The clock is output along with each digital signal having the timing offset defined by the corresponding phase command and the digital signals are captured responsive to the clock and evaluated to determine if each digital signal was successfully captured. A phase adjustment command adjusts the value of each phase command. These operations are repeated for a plurality of phase adjustment commands until respective final phase commands allowing all digital signals to be successfully captured is determined and stored in the storage circuits.
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Harrison Ronnie M.
Johnson Brian
Dorsey & Whitney LLP
Portka Gary
LandOfFree
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